Generic parity generators design using LTEx methodology: A quantum-dot cellular automata based approach

Abstract

Quantum-dot Cellular Automata (QCA) is a prominent paradigm that is considered to continue its dominance in thecomputation at deep sub-micron regime in nanotechnology. The QCA realizations of five-input Majority Voter based multilevel parity generator circuits have been introduced in recent years. However, no attention has been paid towards the QCA instantiation of the generic (n-bit) even and odd parity generator. In this paper, a comprehensive QCA based methodology, termed as LTEx methodology is proposed to produce n-bit even and odd parity generators. The two-input Layered T Exclusive OR (LTEx) module is used to implement high fan-in parity generators. The corollaries first formulate the QCA design metrics such as O-Cost, Cost_α, and irreversible power dissipation and then exploit the operability of the LTEx module to instantiate the efficient n-bit parity generators. These parity generators can exclusively be used in error detection and correction schemes.