A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages

Abstract

<strong>Background and Objectives:</strong> Beside acceptable performance, power consumption and chip area are important issues in embedded systems that should be taken into consideration.<br /> <strong>Methods:</strong> In this paper, a novel continuous-time 1-1 MASH ∆∑ Time-to-digital converter (TDC) is presented. Since the proposed design utilizes 12-bit quantizer based on Gated Switched-Ring Oscillator (GSRO) for both stages, it has been implemented all-digitally. By using a novel structure, only one multi-bit counter is employed for both stages, therefore the required hardware for implementation of this work is much less than conventional TDCs. As a result, complexity, chip area and power consumption would decrease considerably.<br /> <strong>Results: </strong>We implemented the proposed design prototype on an Altera Stratix IV FPGA board. Measured results demonstrate that although this work uses less complex architecture in comparison with previous works, it provides appropriate performance such as 60.7 dB SNR within 8 MHz signal bandwidth at 400 MHz sampling rate while consuming 2.79 mW.<br /> <strong>Conclusion:</strong> Experimental results reveals suitability of the proposed TDC to be incorporated in fast and accurate applications such as ADPLLs and high-resolution photoacoustic tomography. Also, by adjusting the proposed novel structure with more stages higher order of noise-shaping can be attained to enhance SNR and time-resolution further.