A Novel Design of Reversible Multiplier Circuit (TECHNICAL NOTE)

Abstract

Adders and multipliers are two main units of the computer arithmetic processors and play an important role in reversible computations. The binary multiplier consists of two main parts, the partial products generation circuit (PPGC) and the reversible parallel adders (RPA). This paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced PPGC with Peres gates only. Again, an optimized Peres full adder reversible gate is used in RPA part with accompaniment with the carry save adder technique. The comparison of the proposed design with previous ones shows that the proposed reversible multiplier improves the quantum parameters. The proposed design shows lower quantum cost, depth and total cost with the help of a novel design in partial product generator. Moreover, the number of gates, garbage input and output has no change regarding to the best compared design. The proposed multiplier can be generalized as an n×n bit multiplication.