Symmetrical, Low-Power, and High-Speed 1-Bit Full Adder Cells Using 32nm Carbon Nanotube Field-effect Transistors Technology (TECHNICAL NOTE)

Abstract

Carbon nanotube field-effect transistors (CNFETs) are a promising candidate to replace conventional metal oxide field-effect transistors (MOSFETs) in the time to come. They have considerable characteristics such as low power consumption and high switching speed. Full adder cell is the main part of the most digital systems as it is building block of subtracter, multiplier, compressor, and other larger circuits. Therefore, it has a direct impact on the overall performance of the entire digital system. In this paper, we have presented two novel full adder cells using both capacitive threshold logic (CTL) and path transistor logic (PTL). The proposed cells have two symmetrical and identical modules to provide Sum and output carry (Cout). Intensive simulations using Synopsys HSPICE tool are run to evaluate the performance metrics of the proposed cells against some state-of-the-art full adders. Simulations are carried out in the presence of varying power supplies, temperatures, and output loads. Moreover, since process variations are a concern at the manufacturing stage of integrated circuits, we have performed Monte Carlo transient analysis to study the robustness of the proposed cells against diameter variations of carbon nanotubes (CNTs). Simulation results demonstrate that the proposed cells outperform their counterparts and exhibit reasonable results.