A Sub-threshold 9T SRAM Cell with High Write and Read ability with Bit Interleaving Capability

Abstract

This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature decreases write mode failure. An access buffer seperates storage node from read access transistor to improve cell stability and prevent data-related leakage in read operation. Applying virtual ground also reduces the leakage. Furthermore, we design the cell control unit. The simulation results at VDD=0.5V exhibit the effectiveness of our proposed cell compared with other counterparts which are suitable for bit interleaving structure. Comparison results on the proposed cell and 6T cell show our cell improved 70% in write power consumption and 90.45% in read power consumption.