Low cost circuit-level soft error mitigation techniques for combinational logic

Abstract

Following technology scaling trend, CMOS circuits are facing more reliability challenges such as soft errors caused by radiation. Soft error protection imposes some design overheads in power consumption, area, and performance. In this article, we propose a low cost and highly e ective circuit to lter out the e ect of particle strikes in combinational logic. This circuit will result in decreasing Soft Error Propagation Probability (SEPP) in combinational logic. In addition, we propose a novel transistor sizing technique that reduces cost-e ciently Soft Error Occurrence Rate (SEOR) in the combinational logic. This technique generally results in lower design overhead as compared with previous similar techniques. In the simulations run on di erent ISCAS'89 circuit benchmarks, combining the proposed techniques, we achieved up to 70% SER reduction in the overall soft error rate of the circuits for a certain allowed overhead budget.